1. Field of the Invention
The present invention relates to a decoding circuit for a flat panel display, and more particularly to a decoding circuit for a flat panel display wherein a miniaturization is possible by reducing an area of the circuit.
2. Description of Related Art
Recently, a market for electrical appliances and personal computers is steadily increasing as well as a prevalence of portable electronic device such as a notebook computer and a personal communication device. A display device which is a final connection medium between these devices and a user requires a light weight and a low power consumption. Therefore, FPDs (Flat Panel Display) such as an LCD (Liquid Crystal Display), a PDP (Plasma Display Panel) and an OELD (Organic Electro Luminescent Display) instead of a CRT (Cathode Ray Tube) are generally used.
The FPD comprises a panel for actually displaying an image, a row column driving circuit and a column driving circuit. The column driving circuit is alternately referred to as a source driving circuit or a data driving circuit. The column driving circuit converts an image data of a digital format to an image data of an analog format, that is, to a gradation voltage which determines a brightness of a pixel. For instance, in case of a FPD having thirty two gradation voltages, one certain gradation voltage is selected using five bits of data. That is, the column driving circuit sequentially receives the five bits of the data and outputs a selected voltage having one of the thirty two voltage levels. In order to carry out this function, the column driving circuit comprises a decoding circuit for receiving the five bits of the data and outputting the selected voltage having one of the thirty two voltage levels.
FIG. 1 is a diagram illustrating a conventional decoding circuit.
Referring to FIG. 1, the decoding circuit outputs a voltage of thirty two gradation voltages V1 through V32 being outputted from a gradation voltage generator (not shown) corresponding to image data D1 through D5 through an output terminal. Each of gradation voltage terminals having thirty two voltages V1 through V32 inputted therethrough is connected to the output terminal OUT through five n-channel metal-oxide semiconductor field effect transistors (MOSFETs) MN connected in series. One of input data D1 through D5 and inverted input data DB1 through DB5 is applied to a gate of the five MOSFETs MN. Since the inverted input data DB1 through DB5 are applied to the gates of the MOSFETs connected to the gradation voltage terminal where the voltage V1 is applied, the voltage V1 is transmitted to the output terminal only when a data corresponding to “00000” is inputted. In addition, since the input data D1 and the inverted input data DB2 through DB5 are applied to the gates of the MOSFETs connected to the gradation voltage terminal where the voltage V2 is applied, the voltage V2 is transmitted to the output terminal only when a data corresponding to “00001” is inputted. Similarly, since the input data D1 through D5 are applied to the gates of the MOSFETs connected to the gradation voltage terminal where the voltage V32 is applied, the voltage V32 is transmitted to the output terminal only when a data corresponding to “11111” is inputted. The decoding circuit shown in FIG. 1 operates as described above to transmit one of thirty two voltages to the output terminal OUT.
However, the conventional decoding circuit is disadvantageous that the circuit occupies a large area. The reason the decoding circuit occupies the large area is that not only a large number of MOSFETs (32*5=160 in the above example) are used but also an area of each MOSFET is large. The area of each MOSFET tends to increase as a change in a voltage used increases. For instance, if V1 is 0V and V32 is 16V in the above example, the MOSFET should be designed according to a design rule of 2 m. the MOSFET designed according to the design rule has an area a few to tens of times larger than a MOSFET designed according to a design rule of 0.35 m used in a digital circuit having a swing range of 3V. Therefore, the area of the decoding circuit is largely increased.